Computer Aided Design (CAD) and Electronic Design Automation (EDA) problems are conventionally solved with sophisticated but general purpose software tools. Deep learning techniques offer the potential to go beyond these generic tools and train software on company-specific data to learn from company practices and internal knowledge that is not publicly available. “Deep learning” refers to an artificial intelligence function that imitates the workings of biological neural networks in processing data and creating patterns for use in decision making. Deep learning is a subset of machine learning utilizing artificial neural networks capable of learning based on experience, usually, initially, from a training data set. Deep learning is often implemented using deep neural networks. “Deep neural network” refers to an artificial neural network with one or more hidden layers. In addition, after a deep neural network (DNN) has been trained, it may provide faster results than traditional software techniques.
A challenge in applying deep learning (DL) techniques to CAD and EDA problems is mapping the problems into a DL solution space. Representation of netlists is particularly difficult because netlists are a class of directed acyclic graph (DAG) in which each node of the graph is assigned with specific logic block characteristics such as unique combinatorial logic. “Combinatorial logic” refers to logic to convert one or more input signals into output signals. Non-limiting examples of combinatorial logic includes Boolean logic blocks such as AND gates, OR gates, NOR gates etc.; flops, latches, and inverters; and many other types of circuits of varying complexity. “Logic block” refers to combinatorial logic with defined inputs and outputs. “Logic block characteristics” refers to characteristics of a logic block such as power consumption, propagation delay, inputs, outputs, size, and many other possibilities depending on the nature of the logic block and it's use in a circuit. The logic block characteristics may vary according to the class of the logic block: RDL (resistor-diode logic), RTL (resistor-transistor logic), DTL (diode-transistor logic), TTL (transistor-transistor logic), and CMOS, for example. Sub-variants of broad logic block classes may also have logic block characteristics particular to their sub-variant type, e.g. basic CMOS logic vs. advanced CMOS types with optimizations for improving the speed or reducing the power consumption of basic CMOS-class logic blocks. “Directed acyclic graph” refers to a finite directed graph with no directed cycles. That is, it consists of finitely many nodes and edges with each edge directed from one node to another, such that there is no way to start at any node v and follow a consistently-directed sequence of edges that eventually loops back to v again. Equivalently, a directed acyclic graph is a directed graph that has a topological ordering, a sequence of the vertices such that every edge is directed from earlier to later in the sequence. “Netlist” refers to a description of the connectivity of an electronic circuit. In its simplest form, a netlist comprises of a list of the electronic components in a circuit and the circuit nodes (a junction point between two components) that each is connected to. The netlist data must be preprocessed before it can be ingested by a DNN, and the preprocessing step requires human expert considerations and design trade-offs. Some data and structure of the circuit is typically preserved for processing by the DNN; other data and structure may be lost.